In recent years, packaging becomes the performance-limiting factor for microelectronic device, and the issues such as size, weight, cost, pin count, and power consumption are important for packaging design. Therefore, the packaging design generally trade off between material, structure, electronic property to obtain a cost effective and reliable design.
FIG. 1 shows the cross section view of a conventional semiconductor package. The die 10 cut from wafer is attached on the paddle 22 of the leadframe 30 and then adhered to the paddle 22 by epoxy 30 or other viscous adhesives. The resulting structure is then encapsulated by a molding compound 32, thus completing the package.
However, in above-mentioned packaging process, delamination or gap is liable to form between the paddle 22 and the molding compound 32 due to the poor adhesion. Therefore, moisture may be entrapped within the package containing gap or delamination. The package may have the problem of crack when subjected to a following on soldering process due to the thermal expansion of the moisture. Moreover, if the amount of the of the epoxy is excessive, the epoxy is liable to ooze out from under the die and mat cause the occurrence of gap or delamination due to the poor adherence between silver epoxy and molding compound. The gap or delamination also can induce the crack of the package.
As shown in FIGS. 2a and 2b, the silver epoxy 30 should be well controlled such that there is no gap formed between die 10 and die paddle 22.
As shown in FIG. 1b, the size of die paddle 22 should be compatible with that of die 10 to be packaged, therefore, the applicability of this kind of leadframe is limited.
Moreover, the processing time is excessively long because it takes long time to cure the silver epoxy 30.
Another packaging scheme referred as lead on chip (LOC) is proposed to overcome above problems. FIGS. 3a and 3b show shows the cross-sectional view and the top view of LOC package, respectively. In this kind of package, the die 10 is directly attached to the inner lead 24 of leadframe 20 by a binding tape 34 and, accordingly, the provision of die paddle is saved. The adhesive force between the silicone die and the molding compound is superior to that between the lead frame and the molding compound. Therefore, the gap of delamination which may cause pop-corning is prevented in LOC package. Moreover, the die 10 is attached to the inner lead 24 by binding tape 34 in stead of silvery epoxy. The processing time is reduced for the elimination of silver epoxy curing step.
However, as shown in FIG. 3b, the die 10 is attached to the inner lead with tape 34. The bond pads 26 of die 10 are accordingly arranged on somewhat central portion of the die 10 in LOC package.
It is an object of the present invention to provide an improved IC package, which has the same effect as LOC package for preventing pop-corning while the applicability is enhanced.
It is another object of the present invention to provide an improved IC package by which the processing time is reduced.
To achieve above objects, the present provides an IC package wherein at least one tie bar is arranged on the leadframe such that the die to be package is attached to the tie bar by binding tape. The problem of gap or delamination will not occur due to the disuse of silver epoxy and die paddle. The processing time can be reduced and the applicability to die is enhanced.